Analog-to-digital converter systems receive analog signals and convert them to digital representations so that the signals can be processed in the digital domain. One popular architecture for analog-to-digital converter systems is an algorithmic analog-to-digital converter. Algorithmic analog-to-digital converters can be implemented using modern CMOS technology using switched capacitor techniques. In these architectures, capacitor banks are connected to an operational amplifier to form a converter stage. Each stage resolves a number of bits of the digital output word.
The theoretical operation of the analog-to-digital converter relies on the capacitors having the same capacitive value and the amplifier of each stage having an infinite open loop gain. Calibration techniques can be used to account for mismatch in the capacitor values Prior techniques to correct for the finite gain of the amplifier have serious drawbacks. First, many of the amplifier calibration techniques attempted to calibrate the finite gain of the amplifier at the same time they calibrated capacitor mismatch errors. These techniques proved to be very complex and accordingly, very time-consuming in terms of processing effort. Other techniques have necessitated the use of the entire analog-to-digital converter pipeline for calibration operations. These methods used the pipeline for calibration operation and thereby suspend the actual conversion process for some period of time. These techniques typically attempt to recover the loss time through the use of interpolation techniques. As such, the techniques are trading amplification error for interpolation error which may or may not be beneficial.